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Ordering number: EN 5582
LC864532A/28A/24A/20A/16A/12A/08A
CMOS LSI
LC864532A/28A/24A/20A/16A/12A/08A 8-bit Single Chip Microcontroller
Overview
The LC864532A/28A/24A/20A/16A/12A/08A microcontrollers are 8-bit single chip microcontrollers for the TV controls with the following on-chip functional blocks: * CPU : Operable at a minimum bus cycle time of 0.5 s * On-chip ROM maximum capacity : 32K bytes (LC864532A) * On-chip RAM capacity : 256 bytes * CRT display RAM : 160 x 9 bits * On-Screen Display controller Kanji (Chinese character) displaying available * 16-bit timer/counter * 16-bit timer/PWM * 4-channel x 4-bit A/D Converter * Two 6-bit D/A Converters * 8-bit synchronous serial-interface circuit All of the functions above are fabricated on a single chip.
Package Dimensions
unit : mm
3128-DIP52S
[LC864532A, 28A, 24A, 20A, 16A, 12A, 08A]
52 27
15.2 13.8
1 46.0
26
4.25
0.48
1.05
1.78
0.75
0.51min
Feature
(1) Read-Only Memory (ROM) : LC864532A LC864528A LC864524A LC864520A 32768 x 8 bits 28672 x 8 bits 24576 x 8 bits 20480 x 8 bits LC864516A LC864512A LC864508A 16384 x 8 bits 12288 x 8 bits 8192 x 8 bits
(2) Random Access Memory (RAM) :
256 x 8 bits 160 x 9 bits (for CRT display)
(3) Bus cycle time / Instruction-cycle time The LC864532A/28A/24A/20A/16A/12A/08A microcontrollers are constructed to read the ROM twice within one instruction cycle. It has about 1.7 times performance capability within the same instruction-cycle compared to our 4-bit microcontrollers (LC66000 series). The bus cycle time indicates the speed to read ROM.
Bus cycle time 0.5 s 7.5 s Instruction cycle time 1.0 s 15.0 s System clock oscillation Ceramic (CF) Internal RC Oscillation frequency 12 MHz 800 kHz Voltage 4.5 V to 5.5 V 4.5 V to 5.5 V
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters SANYO Electric Co., Ltd. Semiconductor LSI Div. Microcomputer Development Dep.
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
23098HA (II) No. 5582-1/18
3.8
5.1max
SANYO : DIP52S
0.25
LC864532A/28A/24A/20A/16A/12A/08A
(4) OSD functions * Screen for display : 34 columns x 16 rows (at standard character size) * Display RAM : 160 x 9 bits (6 columns for control + 34 columns for display) x 4 rows x 9 bits * 252 kinds of user specified characters 252 kinds 12 x 18 dots * Various character attributes Character colors : 8 colors Character background colors : 8 colors Fringe / shadow : 8 colors Full screen colors : 8 colors Fringe / shadow Rounding * Adjacent character attribute data changing available * Vertical display start line setting in row unit available (row overlapping available) * Horizontal display start position setting available * Eight kinds of character size Horiz. x Vert. = (1 x 1), (1 x 2), (2 x 2), (2 x 4) (1.5 x 1), (1.5 x 2), (3 x 2), (3 x 4) * Shuttering and scrolling in row unit available * Horizontal character pitch selectable : 9 to 16 dots * Polarity of R, G, B, BL output programmable * Polarity of HS, VS input programmable (5) Ports - Input/output ports : 2 ports (16 lines) Input/output port programmable in nibble units : 1 port (8 lines) (when the N-ch open drain output is selected, the data in a bit can be inputted) Input/output port programmable in bit units : 1 port (8 lines) - Input ports : 2 ports (8 lines) (6) A/D converter - 4-channel x 4-bit A/D converter (converted with program) (7) D/A converters - Two 7-bit D/A converters (8) PWM outputs - Ten 7-bit PWMs - 10-channel x 7-bit PWM (9) Timer - Timer 0 : 16-bit timer / counter 2-bit prescaler + 8-bit built-in programmable prescaler Mode 0 : Two 8-bit timers with a programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : 16-bit counter The resolution of Timer is 1 tCYC. - Timer 1 : 16-bit timer / PWM Mode 0 : Two 8-bit timers with a programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit PWM Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : Variable-bit PWM (9 to 16 bits) In Mode 0 and Mode 1, the resolution of Timer and PWM is 1 tCYC. In Mode 2 and Mode 3, the resolution of Timer and PWM selectable : 1 tCYC or 1/2 tCYC by program.
No. 5582-2/18
LC864532A/28A/24A/20A/16A/12A/08A
(10) Remote control receiver circuit (shares with the P73/INT3/T0IN pin) - Noise rejection function - Polarity switching (11) Watchdog timer External RC circuit is required Interrupt or system reset is selectable. (12) Interrupts - 12-source 9-vectored interrupts 1. External interrupt INT0 2. External interrupt INT1 3. External interrupt INT2, Timer/counter T0L (Lower 8 bits) 4. External interrupt INT3 5. Timer/counter T0H (Upper 8 bits) 6. Timer T1H, T1L 7. Serial interface 0 (SIO0) 8. Vertical synchronous signal interrupt (VS) , End of display row 9. Port 0 - Interrupt priority control available Three interrupt priorities are supported (low, high and the highest) and multilevel nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 10 listed above. For the external interrupt INT0 and INT1, high or the highest priority can be set. (13) Sub-routine stack level - A maximum of 128 levels (Sets the stack inside a RAM.) (14) Multiplication/division instruction - 16 bits x 8 bits ( 7 instruction cycle times) - 16 bits / 8 bits ( 7 instruction cycle times) (15) 3 oscillation circuits - On-chip RC oscillation circuit for the system clock - On-chip CF oscillation circuit for the system clock - On-chip LC oscillation circuit for the CRT synchronization (16) Standby function - HALT mode function The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request signals or the system reset. - HOLD Mode The HOLD mode is used to stop oscillations ; the RC (internal) and the ceramic oscillations. This mode can be released by the following conditions. * Pull the reset pin (RES) to low level. * Feed the selected level to either P70/INT0 or P71/INT1. * Feed the Port0 interrupt condition. (17) Factory shipments DIP52S (18) Development Tools - Evaluation (EVA) chip - EPROM with a window - One time ROM version - Emulator
: : : :
LC866098 LC86E4564 LC86P4564 EVA86000 (Main) + ECB864500 (Evaluation board) + POD864500 (Pod)
No. 5582-3/18
LC864532A/28A/24A/20A/16A/12A/08A
System Block Diagram
No. 5582-4/18
LC864532A/28A/24A/20A/16A/12A/08A
Pin Assignment
P10/SO0 P11/SI0/SB0 P12/SCK0 P13 P14 P15 P16 P17/PWM DVSS CF1 CF2 DVDD P90/AN0 P91/AN1 P92/AN2 P93/AN3 RES LC1 LC2 FILT AVDD AVSS DA0 DA1 VS HS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
P07 P06 P05 P04 P03 P02 P01 P00 P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P70/INT0 PWM9 PWM8 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 BL B G R
Top view
No. 5582-5/18
LC864532A/28A/24A/20A/16A/12A/08A
Pin Description
* Port option is able to be specified by a bit unit. Pin Description Table
Pin name DVSS CF1 CF2 DVDD RES LC1 LC2 FILT AVDD AVSS DA0 DA1 VS HS R G B BL PWM0 to PWM9 Port 0 P00 to P07 Pin No. 9 10 11 12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 to 40 I/O -- Input Input -- Input Input Output Output -- -- Output Output Input Input Output Output Output Output Output Function description Negative power terminal for digital circuit Input terminal for ceramic resonator Output terminal for ceramic resonator Positive power terminal for digital circuit Reset terminal LC oscillation circuit input terminal LC oscillation circuit output terminal Filter terminal for PLL Positive power terminal for analog circuit Negative power terminal for analog circuit DA0 output / general purpose I/O terminal DA1 output / general purpose I/O terminal Vertical synchronization signal input terminal Horizontal synchronization signal input terminal Red (R) output terminal of RGB image output Green (G) output terminal of RGB image output Blue (B) output terminal of RGB image output Fast blanking control signal Switch TV image signal and OSD image signal PWM0 to 9 output terminal 15 V withstand 8-bit Input/output port Input/output can be specified in nibble units HOLD release input Interrupt input Pull-up resistor provided/ not provided (in bit units) Output format CMOS/Nch-OD (in bit units) Output format CMOS/Nch-OD (in bit units) Option
45 to 52
I/O
Port 1 P10 to P17
1 to 8
I/O
8-bit Input/output port Input/output can be specified in bit units Other functions P10 SIO0 data output P11 SIO0 data input / bus input / output P12 SIO0 clock input / output 4-bit input port Other functions P70 INT0 input / HOLD release input / Nch-transistor output for watchdog timer P71 INT1 input / HOLD release input P72 INT2 input / timer 0 event input P73 INT3 input (noise rejection filter attached input) / timer 0 event input Interrupt receiver format vector address INT0 INT1 INT2 INT3 Rising enable enable enable enable Falling enable enable enable enable Rising / Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable
Port 7 P70 P71 to P73
41 42 to 44
I/O Input
Pull-up resistor provided/ not provided (in bit units)
Vector 03H 0BH 13H 1BH
Port 9 P90 to P93
13 to 16
Input
4-bit input port Other function A/D converter input port (4 lines)
No. 5582-6/18
LC864532A/28A/24A/20A/16A/12A/08A
* Any port option can be selected in bit units. * Port 0 portion : Pull-up resistor is provided when CMOS output is selected. The pull-up resister is not provided when N-ch Open Drain is selected. * Port 1 option : Programmable pull-up resister is provided when any output form is selected. * Port status during reset
Terminal Port 0 Port 1 Port 7 I/O Input Input Input Pull-up resistor status at selecting pull-up option Pull-up resistor OFF, ON after reset release Programmable pull-up resistor OFF Fixed pull-up resistor provided
* AVDD and AVSS are the power terminals for built-in analog circuit. DVDD and DVSS are the power terminals for built-in digital circuit. Connect them like the following figure to reduce the mutual noise influence.
LSI Power Supply supply DVDD DVSS AVDD AVSS
No. 5582-7/18
LC864532A/28A/24A/20A/16A/12A/08A
Specifications
1. Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Supply voltage Input voltage VDD max VI(1) DVDD, AVDD * P71, 72, 73 * Port 9 * RES, HS, VS R, G, B, BL, FILT PWM0 to PWM9 Ports 0, 1, P70 DA0, 1 Ports 0, 1 * Pull-up MOS transistor output * At each pin * CMOS output * At each pin * CMOS output * At each pin The total of all pins The total of all pins The total of all pins At each pin At each pin At each pin The total of all pins The total of all pins The total of all pins The total of all pins Ta = -30 to +70C -30 -55 DVDD = AVDD min -0.3 -0.3 Ratings typ max +7.0 VDD+0.3 V Unit
Output voltage
VO(1) VO(2)
-0.3 -0.3 -0.3 -2
VDD+0.3 +15 VDD+0.3 mA
Input/output voltage Highlevel output current Peak output current
VIO(1) IOPH(1)
IOPH(2) IOPH(3) Total output current IOAH(1) IOAH(2) IOAH(3) IOPL(1) IOPL(2) IOPL(3) Total output current IOAL(1) IOAL(2) IOAL(3) IOAL(4)
Ports 0, 1 DA0, 1 R, G, B, BL Port 1 Port 0 R, G, B, BL Ports 0, 1 DA0, 1 P70 * R, G, B, BL * PWM0 to PWM9 Port 0 Port 1, P70 R, G, B, BL PWM0 to PWM9 DIP52S
-4 -5 -10 -10 -15 20 30 5 40 40 15 30 430 +70 +150 mW C
Lowlevel output current
Peak output current
Maximum power dissipation Operating temperature range Storage temperature range
Pd max Topr Tstg
*
DVSS and AVSS must be supplied the same voltage, VSS. DVDD and AVDD must be supplied the same voltage, VDD.
VSS = DVSS = AVSS VDD = DVDD = AVDD
No. 5582-8/18
LC864532A/28A/24A/20A/16A/12A/08A
2. Recommended Operating Range at Ta = -30C to +70C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Operating voltage range Hold voltage VDD VHD DVDD, AVDD DVDD, AVDD 0.98 s tCYC tCYC 1.02 s RAMs and the registers hold data at HOLD mode. Output disable Output disable 4.5 to 5.5 4.5 to 5.5 min 4.5 2.0 Ratings typ max 5.5 5.5 V Unit
Input high voltage
VIH(1) VIH(2)
Port 0 (Schmitt) * Port 1 (Schmitt) * P72, 73 * HS, VS * P70 port input / interrupt * P71 * RES (Schmitt)
0.6VDD 0.75VDD
VDD VDD
VIH(3)
Output N-channel transistor OFF
4.5 to 5.5
0.75VDD
VDD
VIH(4)
P70 Output N-channel Watchdog timer input transistor OFF Port 9 DA0, 1 port input Port 0 (Schmitt) Output disable Output disable
4.5 to 5.5
VDD-0.5
VDD
VIH(5) Input low voltage VIL(1) VIL(2)
4.5 to 5.5 4.5 to 5.5 4.5 to 5.5
0.7VDD VSS VSS
VDD 0.2VDD 0.25VDD
* Port 1 (Schmitt) * P72, 73 * HS, VS * Port 9 * P70 port input / interrupt * P71 * RES (Schmitt)
VIL(3)
N-channel transistor OFF
4.5 to 5.5
VSS
0.25VDD
VIL(4) VIL(5) Operation cycle time tCYC(1) tCYC(2)
P70 N-channel transistor Watchdog timer input OFF Port 9 DA0, 1 port input OSD function Except OSD function
4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5
VSS VSS 0.98 0.98 1
0.6VDD 0.3VDD 1.02 30 s
No. 5582-9/18
LC864532A/28A/24A/20A/16A/12A/08A
Parameter Symbol Pins Conditions VDD [V] Oscillation frequency range (Note 1) FmCF CF1, CF2 12 MHz (ceramic resonator oscillation) Refer to Figure 1. 14.11 MHz (LC oscillation) Refer to Figure 2. RC oscillation CF1, CF2 12 MHz (ceramic resonator oscillation) Refer to Figure 3. 4.5 to 5.5 min 11.76 Ratings typ 12 max 12.24 MHz Unit
FmLC
LC1, LC2
4.5 to 5.5
14.11
FmRC Oscillation stable time period (Note 2) tmsCF
4.5 to 5.5 4.5 to 5.5
0.4
0.8 0.02
2.0 0.2 ms
Note 1 : Refer to Table 1 and Table 2 for the oscillation constant. Note 2 : The oscillation stable time is a period necessary for the oscillation to be stable after the power first applied, the HOLD mode released and the main-clock oscillation stop instruction released. Refer to the Figure 3 for details.
No. 5582-10/18
LC864532A/28A/24A/20A/16A/12A/08A
3. Electrical Characteristics at Ta = -30C to +70C , V SS = 0 V
Parameter Symbol Pins Conditions VDD [V] Input high-level current IIH(1) * Port 1 DA0, 1 * Port 0 without pull-up MOS transistor. * Output disable * Pull-up MOS transistor OFF * VIN = VDD (including the off-leak current of the output transistor) VIN = VDD 4.5 to 5.5 min Ratings typ max 1 A Unit
IIH(2)
* Port 7 without pull-up MOS transistor. * Port 9 * RES * HS, VS * Port 1 DA0, 1 * Port 0 without pull-up MOS transistor.
4.5 to 5.5
1
Input low-level current
IIL(1)
* Output disable * Pull-up MOS transistor OFF * VIN = VSS (including the off-leak current of the output transistor) VIN = VSS
4.5 to 5.5
-1
IIL(2)
* Port 7 without pull-up MOS transistor. * Port 9 * RES * HS, VS CMOS output of ports 0, 1 DA0, 1 R, G, B, BL Ports 0,1 Ports 0,1 DA0,1
4.5 to 5.5
-1
IIL(3) Output high-level voltage VOH(1) VOH(2) Output low-level voltage VOL(1) VOL(2)
VIN = VSS IOH = -1.0 mA IOH = -0.1 mA IOL = 10 mA * IOL = 1.6 mA * The total current of the ports 0, 1 is 40 mA or less. * IOL = 3.0 mA * The current of any unmeasured pin is 3 mA or less. IOL = 1 mA VOH = 0.9VDD
4.5 to 5.5 4.5 to 5.5
-1 VDD-1 V
4.5 to 5.5 VDD-0.5 4.5 to 5.5 4.5 to 5.5 1.5 0.4
VOL(3)
* R, G, B, BL * PWM0 to PWM9
4.5 to 5.5
0.4
VOL(4) Pull-up MOS transistor resistance Output off-leakage current Hysteresis voltage Rpu
P70 * Ports 0, 1 * Port 7 PWM0 to PWM9 * Ports 0, 1 * Port 7 * RES * HS, VS All pins
4.5 to 5.5 4.5 to 5.5 13 38
0.4 80 k
IOFF VHIS
VOUT = 13.5 V Output disable
4.5 to 5.5 4.5 to 5.5 0.1VDD
5
A V
Pin capacitance
CP
* f = 1 MHz * Unmeasured input pins are set to VSS level. * Ta = 25C
4.5 to 5.5
10
pF
No. 5582-11/18
LC864532A/28A/24A/20A/16A/12A/08A
4. Serial Input/Output Characteristics at Ta = -30C to +70C , V SS = 0 V
Parameter Symbol Pins Conditions VDD [V] Cycle Lowlevel pulse width Highlevel pulse width Cycle Output clock Lowlevel pulse width Highlevel pulse width tCKCY(1) tCKL(1) * SCK0 * SCLK0 Refer to Figure 5. 4.5 to 5.5 4.5 to 5.5 min 2 1 Ratings typ max tCYC Unit
Input clock
tCKH(1)
4.5 to 5.5
1
Serial clock
tCKCY(2) tCKL(2)
* SCK0 * SCLK0
* Use a pull-up resistor (1 k) during open drain output. * Refer to Figure 5.
4.5 to 5.5 4.5 to 5.5
2 1/2tCKCY
tCKH(2)
4.5 to 5.5
1/2tCKCY
Serial input
Data set-up time Data hold time Output delay time (Serial clock is external clock) Output delay time (Serial clock is internal clock)
tICK tCKI
SI0
* Data set-up to SCK0 rising * Data hold from SCK0 rising * Refer to Figure 5. * Use a pull-up resistor (1k) during open drain output. * Data set-up to SCK0 falling * Data hold from SCK0 falling * Refer to Figure 5.
4.5 to 5.5 4.5 to 5.5
0.1 0.1
s
tCKO(1)
SO0
4.5 to 5.5
7/12tCYC +0.2
s
Serial output
tCKO(2)
4.5 to 5.5
1/3tCYC +0.2
No. 5582-12/18
LC864532A/28A/24A/20A/16A/12A/08A
5. Pulse Input Conditions at Ta = -30C to +70C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] High/low-level pulse width tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIL(4) tPIH(5) tPIL(5) * INT0,INT1 * INT2/T0IN INT3/T0IN (The noise rejection clock is set to 1/1) INT3/T0IN (The noise rejection clock is set to 1/16) RES HS, VS * Interrupt acceptable * Timer0-countable * Interrupt acceptable * Timer0-countable * Interrupt acceptable * Timer0-countable Reset acceptable Display position controllable Each active edge of HS, VS must be more than 1tCYC. Refer to Figure 7. Refer to Figure 7. The monitor point in Figure 10 is 1/2 VDD. 4.5 to 5.5 4.5 to 5.5 min 1 2 Ratings typ max tCYC Unit
4.5 to 5.5
32
4.5 to 5.5 4.5 to 5.5
200 10
s tCYC
Rising/falling time Horizontal pull-in range
tTHL tTLH FH
HS HS
4.5 to 5.5 4.5 to 5.5 15.23 15.73
500 16.23
ns kHz
6. A/D Converter Characteristics at Ta = -30C to +70C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Resolution Absolute precision Conversion time N ET tCAD From Vref selection to when the result is produced (Note 3) 1 bit conversion time = 2tCYC (Regulate the ladder resistor) AN0 to AN3 VAIN = VDD VAIN = VSS 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 min Ratings typ 4 1/4 1/2 1.96 max bit LSB s Unit
Reference current Analog input voltage range Analog port input current
IREF VAIN IAINH IAINL
4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 -1 VSS
1.0
2.0 V DD 1
mA V A
Note 3 : Absolute precision excepts quantizing error (1/2 LSB).
No. 5582-13/18
LC864532A/28A/24A/20A/16A/12A/08A
7. D/A Converter Characteristics at Ta = -30C to +70C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Resolution Absolute precision Settling time Analog input voltage range Output register NDA ETDA tSDA VAOUT RODA DA0 to DA1 (Note 6) 7 bits mode (Note 4) (Note 5) 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 VSS 1.7 4 min Ratings typ 7 1.5 1.0 VDD 7 3 max bit LSB s V k Unit
Note 4 : Note 5 : Note 6 :
Absolute precision excepts quantizing error (1/2 LSB). Settling time refers to the time from when the D/A conversion instruction is executed to when the analog voltage output corresponding to the digital on the specific port is generated. (No load) D/A data = 80H
8. Current Drain Characteristics at Ta = -30C to +70C , V SS = 0 V
Parameter Symbol Pins Conditions VDD [V] Current drain during basic operation (Note 7) IDDOP(1) DVDD, AVDD * FmCF = 12 MHz Ceramic resonator oscillation * FmLC = 14.11 MHz LC oscillation * System clock : CF oscillation * Internal RC oscillation stops * HALT mode * FmCF = 12 MHz Ceramic resonator oscillation * FmLC = 0 Hz (oscillation stops) * System clock : CF oscillation * Internal RC oscillation stops. * HALT mode * FmCF = 0 MHz (oscillation stops) * FmLC = 0 Hz (oscillation stops) * System clock : Internal RC * HOLD mode * All oscillation stops. 4.5 to 5.5 min Ratings typ 16 max 28 mA Unit
Current drain in HALT mode (Note 7)
I DDHALT (1)
DVDD, AVDD
4.5 to 5.5
5
10
mA
I DDHALT (2)
DVDD, AVDD
4.5 to 5.5
400
800
A
Current drain in HOLD mode (Note 7)
I DDHOLD(1) I DDHOLD(2)
DVDD, AVDD
4.5 to 5.5
0.05
20
A
Note 7 :
The currents of the output transistors and the pull-up MOS transistors are ignored.
No. 5582-14/18
LC864532A/28A/24A/20A/16A/12A/08A
Oscillation type 12 MHz ceramic resonator oscillation Manufacturer Murata Oscillator CSA12.0MTZ CST12.0MTW Kyocera KBR-12.0M C1 33 pF C2 33 pF
on chip 22 pF 22 pF
* Both C1 and C2 must use a K rank (10%) and SL characteristics. Table 1. Ceramic Resonator Oscillation Guaranteed Constant (main-clock)
Oscillation type 14.11 MHz LC oscillation
L 4.7 H 4.7 H10% (Variable)
C3 33 pF 33 pF
C4 45 pF (Trimmer) 33 pF
* See Figures 10 and 11 for the oscillation frequency. Table 2. LC Oscillation Guaranteed Constant (OSD clock) (Notes) * Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest pattern length. * If you use other oscillators herein, we provide no guarantee for the characteristics. * Adjust the voltage of monitor point in Figure 10 to 1/2VDD10% by the LC oscillation constant 'L' or 'C' to lock the PLL circuit.
main clock Figure 1 Ceramic Resonator Oscillation
OSD clock Figure 2 LC Resonator Oscillation
No. 5582-15/18
LC864532A/28A/24A/20A/16A/12A/08A
VVDD DD VDD lower limit VDD limit 0V 0V
Power supply Reset time RES Internal RC resonator oscillation tmsCF CF1, CF2
Operation mode
Unfixed
Reset
Instruction execution mode
< Reset time and oscillation stable time. > HOLD release signal Valid
Internal RC resonator oscillation tmsCF CF1, CF2
Operation mode
HOLD
Instruction execution mode
< HOLD release signal and oscillation stable time. >
Figure 3 Oscillation Stable Time
VDD VDD RRES RES CRES (Note)Set the valuesof C , R Fix value of CRES, RRESso that is that (Note) RES RES sure to reset untill 200 s, after Power the reset time is 200 s or longer. supply has been over inferior limit of supply voltage.
Figure 4 Reset Circuit No. 5582-16/18
LC864532A/28A/24A/20A/16A/12A/08A
0.5 VDD 0.5VDD
< AC timing point >
tCKCY tCKL Serial clock tICK Serial input tCKO Serial output < Timing >
Figure 5 Serial Input/output Test Condition
VDD VDD
tCKH 1K tCKI
50pF
< Test load >
tPIL
tPIH
Figure 6 Pulse Input Timing Condition - 1
tPIL (5)
0.75VDD 0.75VDD 0.25VDD 0.25VDD
tPIH (5)
0.75VDD 0.75VDD 0.25VDD 0.25VDD
tTLH
tTLH t
tPIL (5)
1tCYC
1tCYC
(a) In case of active low (b) In case of active high Figure 7 Pulse Input Timing Condition - 2
LC864500
10 k HS HS
2S C536
Figure 8 Recommended Interface Circuit No. 5582-17/18
LC864532A/28A/24A/20A/16A/12A/08A
Monitor point
22 k
FILT + 2.2 F 1000 pF
Figure 9 FILT Recommended Circuit (Note) * Place the parts connected to the FILT terminal as close to the FILT as possible with the shortest pattern length on the board.
VDD = 5 . 0 V VDD
16
L = 4.7H C = C1 = C2 Ta = 2 5 C C = 30pF
16
VDD = 5.0V VDD
C1 = C2 = 33pF Ta = 25C
15
L = 4.5H
C = 33pF C = 36pF
15
L = 4.7H L = 4.9H L = 5.1H
14
C = 39pF
14
13
13
0
1
2
3
4
5
0
1
2
3
4
5
Figure 10 FILT-LC Oscillation Frequency (1)
Figure 11 FILT-LC Oscillation Frequency (2)
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1998. Specifications and information herein are subject to change without notice.
PS No. 5582-18/18

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